1. Field of Art
This disclosure generally relates to the field of digital circuit design, and more specifically to phase selectors used in phase locked loops.
2. Description of the Related Art
A phase locked loop (PLL) is a common circuit used in many clock circuits. One common use of a PLL, shown in FIG. 1A, is to take a low speed reference clock 101 and produce a high speed clock 109 whose frequency is an integral multiple R of the low speed clock. In FIG. 1A, a divider 106 divides the output clock 109 by integer R to produce a low speed clock 102. The phase frequency detector (PFD) 103 compares the low speed clock 102 to the reference clock 101. The output of PFD 103 is coupled to the input of the PLL loop filter 104. The output 108 of the loop filter 104 is coupled to the control of the VCO 105. The loop filter 104 adjusts the VCO 105 so that its frequency is closer to the desired multiple R of the input clock 102.
It is often desirable to make small, frequent, deterministic changes to the PLL output frequency to implement functions such as spread spectrum, where the high speed clock frequency is constantly varied by a small amount to reduce electromagnetic interference. FIG. 1B illustrates a phase mixer 112 that has been added to the PLL feedback path in order to implement spread spectrum. A phase mixer 112 adds small phase changes to its input clock 109, sometimes as small as 0.2% of a period, to produce its output clock 110. These small phase changes result in small frequency changes. The design and use of phase mixers for this type of application is well known in the art.
One problem with phase mixers is that they tend to use a lot of area and power and are susceptible to power supply noise induced jitter. Also, despite the fine phase resolution of the phase mixer, most of their uses in PLLs require large phase steps; the ability to take fine phase steps is not needed.